Generally in computer systems, and especially in personal computer systems, data is transferred between system devices such as a central processing unit (CPU), memory devices, memory controllers and various input/output (I/O) devices. The memory devices may include system memory, memory located on the various I/O devices, or expansion memory which may be added to the system in the form of plug-in adapter cards. Typically, the system or expansion memory includes dynamic random access memory (DRAM) devices.
The use of DRAM devices as memory devices in computer systems is widespread, due in part to the reasonable cost of DRAM devices as compared to other memory devices. DRAM devices also offer the benefit of not requiring back-up power to store information therein. Rather, information is stored in the form of electrical charge which represents data. The memory structure of the DRAM comprises matrices of capacitors for storing the electrical charge. Information is represented by the presence or absence of electrical charge in these storage capacitors.
Although DRAM devices do not require battery back-up power to retain their contents, the charge storing capacitors located therein need to be periodically refreshed in order to retain the stored information. The charge stored in the DRAM storage cells is rather minimal, and is prone to leak from the storage capacitors over time, resulting in data which may eventually be corrupted. Unless the DRAM devices are refreshed, stored data may be permanently lost.
In a typical refresh cycle, the data represented by the charged capacitors in the DRAM is periodically read out, amplified, and written back to the DRAM to prevent data corruption. Refresh cycles occur at a specific frequency and operate for a particular duration. Typically, the DRAM device manufacturer will specify a time period during which a refresh cycle must occur to insure against data corruption. The duration of the refresh cycle operating at this specified frequency depends on the type of DRAM devices incorporated into the system. Typically, DRAM incorporated into system memory on the system planar is capable of being refreshed faster than DRAM which resides on the various I/O devices or expansion memory which optionally may be added to the system.
The storage capacity of DRAM devices which can be supported within system memory has increased over the years, as has the speed of these DRAM devices. For example, the system memory available on an IBM AT bus architecture is 16 megabytes and is capable of being refreshed during access periods on the order of 70 nanoseconds. Accordingly, the need for optional expansion memory to supplement the system memory has decreased. Present methods of refreshing DRAM devices, however, do not distinguish between systems with and without expansion DRAM, relying instead on refresh cycles which are slow enough to accommodate both types of DRAM in the systems.
Accordingly, it is an object of the present invention to provide a method and logic for refreshing DRAM devices in a computer system which takes advantage of advances in system memory architecture by providing two speeds at which refresh cycles may operate in the system, depending upon whether or not optional DRAM memory is installed in the system.